For reasons which are well established in the practice of digital signal processing, it is usually desirable to perform arithmetic computations on numbers which are represented in 2's complement form. In such a form positive numbers are represented by a sign bit (0) and bits representing the magnitude of the number whereas a negative number has a sign bit of unity (1) and bits representing the 2's complement of the magnitude. As is well known, the 2's complement form of a number is formed by taking the 1's complement of the number, by changing each zero to a 1 and vice versa, and adding unity at the least significant bit position. The 2's complement system is very convenient for the representation of negative numbers because the operation of subtraction may be performed implicitly by the actual performance of addition.
In networks composed of 2's complement integer arithmetic operators which share a common data transmission format, there is often a requirement to maximise the use of available numerical resources. Additive operators can cause a single bit word growth, which must counteracted by single bit arithmetic downshifting if overflow is to be avoided. Arithmetic downshifting introduces an error which can be minimised and made zero-mean by the operation of `rounding`. Rounding is essentially the action of adding one bit (i.e. incrementing) at the significance of the discarded bit before that bit is discarded. While this is trivial to achieve in the case of an adder, with no penalty in relation to the area occupied by the circuits or time delay, it is more difficult to achieve in relation to a subtracter.
As is well known, subtraction of a number may be performed by 1's complementing the number, adding the number and then adding an incrementing bit at the least significant bit position. This requires only one carry propagation but its achievement requires the operation of incrementing. In a serial data system, the corresponding bits of two numbers which are to be added (or subtracted) are fed synchronously to an adder (or subtracter), normally starting with the least significant bit, and the incrementing is performed in response to a LSB control signal.
The present invention however concerns incrementing subtraction. Whereas simple subtraction may be represented as the formation of the quantity (A-B), incrementing subtraction may be represented as the formation of the quantity (A-B+1) or the quantity -(A+B). The former requires an incrementing operation additional to that required for two's complementing (-B). The latter (usually termed `negating addition`) also requires an additional incrementing operation. There is therefore the considerable problem of how to provide an incrementing subtractive circuit, e.g. an incrementing subtracter or negating adder, which requires a incrementing operation additional to that necessary for simple subtraction. The difficulty arises from the existence of, apparently, only one opportunity, namely the time of the least significant bit, for incrementing.